1. Field of the Invention
The present invention relates to a solid-state electrolytic capacitor for use in a decoupling capacitor that is mainly used in power circuits of electronic apparatus. In particular, the invention is suitably applied to a solid-state electrolytic capacitor having three or more mounting terminals.
2. Description of the Related Art
With the recent miniaturization and the increase in functionality of electronic apparatus, the number of pins, the processing speed, and the transmission speed are increasing in semiconductor devices as components of electronic apparatus. Such electronic apparatus have a printed circuit board that is mounted with packages incorporating semiconductor devices. Among such printed circuit boards, ones mounted with a large number of passive components to enable normal operation of semiconductor devices are increasing rapidly; the number of components is increasing in such printed circuit boards. Many of those passive elements are capacitors.
A first role of the capacitor is to smooth out noise such as switching noise that is superimposed on a supply voltage. A second role is the role of a decoupling capacitor which prevents outflow of high-frequency noise occurring in a processor to the entire printed circuit board. A third role is to prevent a voltage drop by supplying a large amount of current in a short time when the operation mode of a processor is switched.
One known capacitor is a stacked capacitor that is formed by stacking solid-state electrolytic capacitor elements (refer to JP-A-2006-40938 as Patent Document 1). In this stacked capacitor, solid-state electrolytic capacitor elements of the same kind are stacked so as to be connected to each other in parallel.
For a capacitor to play its roles effectively, it is indispensable to control its equivalent series inductance (hereinafter abbreviated as ESL) to a small value. A common measure to control the ESL to a small value is to mount a large number of capacitors in such a manner that they are wired parallel with each other.
Large-scale integrated circuits (hereinafter abbreviated as LSIs) are mounted on circuit boards of electronic apparatus. The operation frequency of LSIs is on the order of hundreds of megahertz to gigahertz and the clock rise time is becoming very short. If the load of an LSI is increased rapidly, the parasitic resistance and the parasitic inductance between interconnections that connect the LSI to power sources are increased, causing the voltages supplied to the LSI to drop. This leads to a problem of erroneous operation of the LSI. One conventional measure to reduce such a voltage drop is to dispose a stacked ceramic capacitor as a decoupling capacitor near the LSI. This attains noise reduction.
As exemplified above, stacked ceramic capacitors are frequently used as decoupling capacitors. The capacitance of stacked ceramic capacitors tends to decrease to a large extent when a bias voltage is superimposed or the temperature of the operation environment is increased. To prevent capacitance reduction of decoupling capacitors, it is necessary to mount a number of reserve stacked ceramic capacitors. This is a major factor in increase of the number of components.
One known measure to reduce power source noise generated by a semiconductor device that is mounted in an electronic apparatus is to form a capacitor as close to the semiconductor device as possible. To this end, it has been proposed to incorporate a capacitor in an interposer board of a semiconductor package (for example, refer to JP-A-2006-216755 as Patent Document 2).
Incidentally, among factors in ESL increase are the permeability of conductors inside a device and the lengths and shapes of interconnections from the inside of the device to mounting terminals For example, in order to reduce an impedance part, the following techniques have come to be employed frequently in this connection. First, an inductance component called loop inductance which occurs between positive and negative mounting terminals is reduced by making those terminals closer to each other. Second, mounting terminals are increased and positive and negative terminals are arranged linearly and alternately or arranged two-dimensionally in a checkered manner.
JP-A-2002-343686, which will be hereinafter referred to as Document 3, proposes a solid-state electrolytic capacitor which has a valve metal sheet member, a dielectric coating formed on a porous portion of the valve metal sheet member, a solid-state electrolytic layer formed on the dielectric coating, and a collector layer formed on the solid-state electrolytic layer. The valve metal sheet member has an electrode portion on one surface. The metal sheet member further includes plural holes formed through the valve metal sheet member so as to extend from the electrode portion side or the collector layer side to the collector layer or the electrode portion and are filled with respective insulators. Conductors are disposed at the centers of the holes so as to be electrically connected to the collector or the electrode portions. This solid-state electrolytic capacitor has an advantage that high-frequency response characteristics such as ESR and ESL of an actual circuit using it can be improved by decreasing terminal length and wiring lengths.
JP-A-10-97952, which will be hereinafter referred to as Patent Document 4, proposes a capacitor-incorporated wiring board in which a capacitor is incorporated in a wiring board. This reference states that the capacitor provided in the wiring board is relatively thin and has a large capacitance and it is possible to build-up similar capacitor elements.